1. Field of the Invention
Embodiments of the invention relate to a method of programming a nonvolatile memory device. More particularly, embodiments of the invention relate to a method of programming a nonvolatile memory device through hybrid boosting using both self-boosting and local boosting.
2. Discussion of Related Art
A nonvolatile memory device, for example a flash memory, is electrically erasable and programmable and can preserve data even in the absence of power. One type of flash memory is a NAND type which has a string structure in which a plurality of flash memory cells is connected in series. NAND type flash memories can be easily integrated in and supplied at a low cost making it a typical choice for use in a variety of portable electronic devices.
Cell transistors of a flash memory are erased according to an F-N tunneling mechanism. In particular, a cell transistor is erased by applying a ground voltage to the control gate of the cell transistor and applying a voltage higher than a power supply voltage to a semiconductor substrate (or bulk). Under this erase bias condition, a large voltage difference between the floating gate and the bulk forms a strong electric field between the floating gate and the bulk. As a result, electrons existing in the floating gate region are discharged to the bulk according to the F-N tunneling effect and the threshold voltage of the erased cell transistor is shifted in the negative direction.
Cell transistors of a flash memory are programmed by applying a voltage, higher than the power supply voltage, to the control gate of the cell transistor and a ground voltage is applied to the drain of the cell transistor and the bulk. Under this bias condition, electrons are injected into the floating gate of the cell transistor according to the F-N tunneling effect. The threshold voltage of the programmed cell transistor is shifted in the positive direction.
FIG. 1 is a block diagram of a NAND type flash memory device 100 including memory cell array 110, row decoder 130 and page buffer circuit 150. Memory cell array 110 includes a plurality of memory blocks (not shown) each having a plurality of strings 110_1-110_M in a column direction. FIG. 1 illustrates only one memory block for convenience of explanation. Each of the strings 110_1 -110_M includes a string selecting transistor SST, a ground selecting transistor GST and a plurality of memory cell transistors MCT<0>-MCT<N-1> which are serially connected between string selecting transistor SST and ground selecting transistor GST. The gate of string selecting transistor SST is connected to string selection line SSL and the drain of string selecting transistor SST is connected to a bit line (BLe or BLo). The gate of ground selecting transistor GST is connected to a ground selection line GSL and the source of ground selecting transistor GST is connected to a common source line CSL. The control gates of the plurality of memory cell transistors MCT<0>-MCT<N-1> are respectively connected to wordlines WL<0>-WL<N-1>.
The voltages of the string selection line SSL, the wordlines WL<0>-WL<N-1> and the ground selection line GSL are controlled by row decoder 130 in response to a predetermined timing control signal (not shown). The voltages of the bit line pair BLe and BLo are respectively controlled by page buffers (not shown) included in page buffer circuit 150. The operation of controlling the string selection line SSL, the wordlines WL<0>-WL<N-1>, the ground selection line GSL and the operation of controlling bit line pair BLe and BLo are well known.
FIG. 2 is a graph illustrating the relationship between a cell state and a cell voltage in a multi-level nonvolatile memory device. Reference 11 represents an erased state and 10, 00 and 01 represent a programmed state. The erased state is distinguished from the programmed state by the threshold voltage of a cell transistor. The operation of erasing or programming cell transistors of a multi-level nonvolatile memory device is well known in the art. Self-boosting is a typical method of programming a nonvolatile memory device. FIG. 3 is a timing diagram illustrating the self-boosting method. The operation of programming a cell transistor will be explained with reference to FIGS. 1, 2 and 3. The control gates of cell transistors MCT<0>-MCT<N-1> are respectively connected to wordlines WL<0>-WL<N-1>. Referring to FIG. 3, a pass voltage VPASS, which is lower than a program voltage VPGM, is applied to the control gates of cell transistors MCT<0>-MCT<N-1> in an initial period B of the programming operation. In period C, program voltage VPGM is applied to a selected cell transistor MCT<I> to program the cell. All the cell strings included in a single memory block are commonly connected to wordlines WL<0>-WL<N-1>. Accordingly, when a selected cell transistor is programmed, the program voltage is also applied to the cell transistors of the other cell strings connected to the selected cell transistor so that the states of the cell transistors of the other cell strings are likewise disturbed.
FIG. 4 is a diagram for explaining program disturbance that can occur in a cell string in which all the cells (cell transistors) are erased in a self-boosting method. FIG. 5 is a diagram for explaining program disturbance that can occur in a cell string in which parts of the cells are programmed in the self-boosting method. FIGS. 4 and 5 illustrate neighboring cell strings where each cell string includes 32 cell transistors, a program voltage is applied to the twenty-ninth wordline WL<28> to program memory cells X and Z, and lower memory cells are programmed first. Referring to FIG. 4, 0V is applied to a cell string (program string) including a cell X that is to be programmed through bit line BLo and a program voltage VPGM is applied to the cell string through the wordline WL<28> to program cell X. A power supply voltage VCC is applied to a cell string (inhibited string) including cell W connected to the same wordline WL<28> to which cell X is connected through bit line BLe and the program voltage VPGM is applied to the inhibited string through wordline WL<28>. A boosting channel, which has a high voltage maintained according to a boosting voltage caused by a pass voltage VPASS applied to the wordlines other than the wordline WL<28> and a boosting voltage caused by the program voltage VPGM, is formed in the bulk of the inhibited cell string. Consequently, F-N tunneling is inhibited in cell W to disturb programming of cell W. The cells located under cell W are erased. The threshold voltages of the cell transistors have a negative value in the erased state, as illustrated in FIG. 2, so that boosting efficiency in the cell string including the cell transistors is improved. Accordingly, a high voltage sufficient to inhibit F-N tunneling is maintained in cell W.
As illustrated in FIG. 5, when cells located under a cell Y connected to the same wordline WL<28> to which the programmed cell Z is connected are programmed, the threshold voltages of cell transistors has a predetermined positive value so that boosting efficiency in the cell string including the cell transistors is decreased. Accordingly, F-N tunneling may occur in cell transistor Y under certain circumstances. It is assumed that the cells located under cell Y are programmed to 00. However, the cells can be programmed to other states.
When the cells located under cell Y are programmed to 00, the boosting voltage according to the program voltage VPGM in cell Y and the boosting voltage according to pass voltage VPASS in the cells located above cell Y are maintained high. However, boosting efficiency according to pass voltage VPASS in the cells under cell Y is decreased so that the voltage of the bulk of the cell string is reduced according to a charge sharing effect. A boosting channel having a low voltage is formed in the bulk of the cell string.
Accordingly, the bulk voltage in cell Y is decreased and a high program voltage VPGM is applied to wordline WL<28> connected to cell Y which programs cell Y that was not intended to be programmed This phenomenon is referred to as program disturbance. Particularly, when programming is performed from lower cells to upper cells, the program disturbance is aggravated when a selected cell is close to the upper cells because the number of cells bringing about charge sharing is increased. Therefore, there is a need to prevent the program disturbance when programming a nonvolatile memory device.